- page fault on reserved bit error (in pde/pte) is never handled,
  reserved bit errors are fatal errors.

- no execute disable bit. ED requires refactorisation of 
  Memory_access and the page-directory traversal.

- how to model CR?, EFLAGS, memory mapped devices (APIC?)

- how to model avail. bits in page tables
  - the page table walker needs to write the envelope datatype 
    but using nested pods to model the type of the available
    bits in the page table result in type mismatches.
  Ideas:
    - initialize processor with avail. bit type
    - use uniform type which can be used for the access without 
      destroying the embedded type.

- The evaluation order of C++ expressions is as defined by the state
  transformers in expressions.pvs.  (Note that the C++ standard leaves the
  evaluation order mostly implementation specific.)  This can be achieved at
  the source level by introducing artificial sequence points and disallowing
  operands with side effects: e.g.
    x = f() + g();
  is equivalent to either
    t1 = f();
    t2 = g();
    x = t1 + t2;
  or
    t1 = g();
    t2 = f();
    x = t1 + t2;

- The PVS definition of some C++ expressions deviates from what the C++
  standard specifies, or defines implementation-specific behavior.  See
  expressions.pvs for details.  Such expressions must not be used in a way
  where the difference would matter.

- Physical Memory must not have side effects that cross minimal page
  size (4K) boundaries:
  To incorporate address translation into linear side effects we split 
  the linear list access into multiple list accesses where each is
  contained within a 4KB page. This side effects in the underlying
  physical memory which cross page boundaries would not be applied. 
